1. Field of the Invention
The invention relates to a power-on reset circuit and a method thereof, and more particularly to a power-on reset circuit for use in a chip with low operation voltage and a method thereof.
2. Description of the Related Art
In general, there are two methods for generating reset signal at power-on state. One method is to generate the reset signal by a RC delay unit, as shown in the circuit schematic illustration in FIG. 1 and the associated voltage diagram in FIG. 2. The other method is to generate the reset signal by using the threshold voltage of an active device, as shown in the circuit schematic illustration in FIG. 3 and the associated voltage diagram in FIG. 4.
Referring to FIG. 1, the power-on reset circuit includes an RC (resistor & capacitor) voltage divider 11 and a comparator 12. The RC voltage divider 11 includes a resistor 111 and a capacitor 112 and generates an output voltage VRC. The RC voltage divider 11 is connected to a voltage source VDD and a ground 13. The comparator 12 receives an input voltage αVDD proportional to the voltage source VDD and the output voltage VRC of the RC voltage divider 11 and generates a reset signal Reset by comparing VRC with αVDD. At the beginning of power on, voltage VRC<αVDD and the comparator enables the reset signal Reset, such as outputting a High State. Then, when voltage VRC>=αVDD, the comparator disables the reset signal Reset, such as outputting a Low state. As shown in the clock diagram in FIG. 2, when the power is on, the voltage source VDD outputs a transient voltage having a magnitude increasing from 0 as time elapses. At the beginning of power on, voltage VRC<αVDD and the comparator enables the reset signal Reset. At the time when the condition of (VRC<αVDD) is changed to the condition of (VRC>=αVDD), the reset signal Reset is disabled.
Referring to FIG. 3, a power-on reset circuit includes a resistor—metal oxide semiconductor voltage divider 21 and a comparator 22. The resistor—metal oxide semiconductor voltage divider 21 includes a resistor 211 and a metal oxide semiconductor 212 and generates an output voltage Vth. The resistor—metal oxide semiconductor voltage divider 21 is connected to a voltage source VDD and a ground 23. The comparator 22 compares an input voltage αVDD proportional to the voltage source VDD to the threshold voltage Vth and generates a reset signal Reset by comparing VRC with αVDD. When the threshold voltage Vth is greater than the input voltage αVDD, the comparator 22 enables the reset signal Reset. However, when the threshold voltage Vth<=αVDD, the comparator 22 disables reset signal Reset to end the reset state. As shown in FIG. 4, at the beginning of power on, the voltage source VDD outputs a transient voltage having a magnitude increasing from 0 as time elapses. At the beginning, the threshold voltage Vth>αVDD, the comparator enables the reset signal Reset. At the moment when the condition of (Vth>αVDD) is changed to the condition of (Vth<=αVDD), the reset signal Reset is disabled.
However, the above-mentioned conventional power-on reset circuits have the following drawbacks. Usually, for the RC delay circuit, an external capacitor is needed to have enough delay time. For the circuit with the active device, such as the metal oxide semiconductor, the threshold voltage of the active device tends to be changed with the process variation, environment temperature variation, and other conditions. Thus, the conditions of reset signal being disabled are not consistent and may be changed with the variation of the various environment conditions. Consequently, errors may be caused in which the reset signal cannot be disabled, or is not disabled at the proper time. In addition, as the operation voltage of the IC chip gets lower and lower, the operation voltage VDD gets smaller and smaller. Therefore, when the power is on, the transient voltage variation gets smaller and smaller, and thus the tolerance of the threshold voltage variation gets smaller and smaller. Thus, the conventional power-on reset circuits are not suitable for use in the chip with the low operation voltage.